The present invention relates to a system for refreshing the contents of dynamic memories associated with a data processor.
It is a common practice that semiconductor memories are employed for the main memory of an electronic computer system, for example, a microcomputer. In this case, the dynamic memory is more often used that the static memory, because of the suitability of the dynamic memory ascribable to its nature, and its low cost. The dynamic type semiconductor memory, however, suffers from the fact that the memory contents are volatilized in a fixed time period (about several milliseconds). This necessitates the refreshing of the memory contents at a predetermined time interval.
In the case of the most popular type dynamic memory of 4 K words .times. 1 bit, i.e. of 4096 bits, for example, the refreshing operation is made in such a manner that the memory cells of 64 in row are first refreshed and this refreshment is repeated sixty-four times in column direction, because of the 64 .times. 64 matrix of such memory construction. The memory cells of the 4096 bits are addressed by applying a binary-coded address signal binary-coded to 12 address lines, because of 2.sup.12 = 4096. The refreshing of the memory cells may also be performed by using the address lines. More specifically, the refreshing operation is periodically performed by one of the grouped lines. That is, 12 address lines are divided into two groups each consisting of 6 lines.
The construction of the refreshing system using such dynamic memory device is in a block form shown in FIG. 1. In the figure, reference numeral 1 designates a dynamic memory, 2 a refresh circuit, and 3 a control circuit for the whole of the dynamic memory 1 (for example, 4096 bits). The control circuit 3 also controls the data flow between the dynamic memory 1 and a central processing unit which is abbreviated as CPU 4. The refreshing operation of the refreshing system is time-charted in FIG. 2. FIG. 2(a) shows an operating condition of the dynamic memory 1, in which A is the time-period required for the memory 1 to be refreshed, and B is the time-period permitting the memory 1 to be accessed from exterior. FIG. 2(b) shows a kind of ready signal from the control circuit 3 to the CPU 4. When the ready signal of FIG. 2(b) is a logical level "1," the memory 1 is under an operable condition. In other words, the CPU 4 is freely accessible to the memory 1. Conversely, when the logical level of the ready signal is "0," the dynamic memory 1 is being refreshed and the CPU 4 is prohibited from accessing to the memory 1. The operation as shown in the time chart in FIG. 2(b) must be repeated every N ms because of the proper characteristic of the semiconductor dynamic memory used. Accordingly, the CPU 4 is prohibited from the operation of program execution every time-period A. The result is that the data processing efficiency of the electronic computer system is reduced.